/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2012-2020.
 * Description: Linux GMAC debugging Ethernet port driver
 * Author: yanbo
 * Create: 2012-12-25
 */
#ifndef GMAC_GMAC_H
#define GMAC_GMAC_H

#define GMAC_OK                     0
#define GMAC_ERROR                  (-1)

#define SGMII_1000M			   		0x2
#define SGMII_100M			   		0x1
#define SGMII_10M			   		0x0

#define MAX_MAC_PORT_NUM            1
#define MAC_10M_MII                 0
#define MAC_100M_MII                1
#define MAC_10M_SGMII               6
#define MAC_100M_SGMII              7
#define MAC_1000M_SGMII             8

/* Minimum MTU value */
#define MIN_MTU_LEN					68

/* System control register */
/* eth device name, such as platform device name */
#define GMAC_DEV_NAME       		"hip04-ether"

/* 485 FPGA model PPE_COMMON address mapping */
#define GMAC_PPE_COMMON_BASE        (0xf2890000)
#define SC_BASE_ADDR			    (0xf28f5000)
#define IOCONFIG_BASE_ADDR		    (0xf040c000)
#define IO_BASE_ADDR			    (0xf0400000)
#define GMAC_PPE_COMMON_SIZE        0x10000

/* 485 FPGA model in PPE_TNL_11 base address mapping */
#define GMAC_DEV_IOBASE             (0xf2880000)
#define GMAC_DEV_IOSIZE             0x10000
/* 485 FPGA model in PPE_TNL_11 interrupt ID */
#define GMAC_DEV_IRQNUM             (205)

#define gmac_writel(value, addr)    do { dsb(); writel((value), (void __iomem *)(uintptr_t)(addr)); dsb(); } while (0)
#define gmac_readl(addr)            readl((void __iomem *)(uintptr_t)(addr))
#define gmac_iounmap(addr) 			iounmap((void __iomem *)(uintptr_t)(addr))
#define gmac_ioremap(addr, size) 	((unsigned long)(uintptr_t)ioremap((addr), (size)))

/* DIR LEVEL */
#define LOW_LEVEL 					0
#define HIGH_LEVEL 					1
#define INPUT_PIN 					0
#define OUTPUT_PIN 					1

#define HI_CPU_GPIO_INPUT_REG       (0x50)
struct board_info {
	unsigned long gmac_iobase; /* The board uses the GE base address */
	unsigned long gmac_irqnum; /* The board uses the GE interrupt ID */
};

struct board_info hi1381_ubbp_d = {
	.gmac_iobase = 0xf2830000,
	.gmac_irqnum = 200,
};

struct board_info hi1381_ubbp_v2 = {
	.gmac_iobase = 0xf2830000,
	.gmac_irqnum = 200,
};

/******************************************************************************/
/* GMAC PPE register defined */
/******************************************************************************/
#define GE_AN_NEG_STATE								(0x58)

/* PPE_CFG_WE_ADDR is the write address of the POE. */
#define PPE_CFG_WE_ADDR_REG                         (0x0)
/* PPE_CFG_BMU_ADDR for BMU and releases the buffer base address. */
#define PPE_CFG_BMU_ADDR_REG                        (0x4)
/* PPE_CFG_RX_BUFFREQ_TIMER for receiving buffer timeout register. */
#define PPE_CFG_RX_BUFF_REQ_TIMER_REG               (0x8)
/* Access the BMU and POE PPE_CFG_VMID is VMID. */
#define PPE_CFG_VMID_REG                            (0xC)
/* PPE_CFG_QOS_DROP_EN is 32 POOL by QoS packet loss enable */
#define PPE_CFG_QOS_DROP_EN_REG                     (0x10)
/* PPE_CFG_TM_ADDR is packet loss register address of the TM, this address push package,TM is discarded. */
#define PPE_CFG_TM_ADDR_REG                         (0x14)
/* PPE_CFG_REQ_BMU_OUT_DEPTH to the BMU application cache outstanding depth. */
#define PPE_CFG_REQ_BMU_OUT_DEPTH_REG               (0x18)
/* PPE_CFG_CMM_TO_BE_RST is the channel is to be reset. */
#define PPE_CFG_CMM_TO_BE_RST_REG                   (0x1C)
/* PPE_CFG_MEM_TIMING is PPE MEM timing configuration. */
#define PPE_CFG_MEM_TIMING_REG                      (0x20)
/* PPE_CFG_BP_BUS_TIME is PPE backpressure bus timeout configuration register. */
#define PPE_CFG_BP_BUS_TIME_REG                     (0x24)
/* PPE_CFG_RX_CFF_ADD is 32 x POOL FIFO passive assigned BUF address,
 * 0x0100~0x017C are POOL0~POOL31 FIFO passive allocation BUF address corresponding to
 */
#define PPE_CFG_RX_CFF_ADDR_0_REG                   (0x100)
/* PPE_CFG_RX_CFF_ADD is 32 x POOL FIFO passive assigned BUF address,
 * 0x0100~0x017C are POOL0~POOL31 FIFO passive allocation BUF address corresponding to
 */
#define PPE_CFG_RX_CFF_ADDR_1_REG                   (0x104)
/* PPE_CFG_RX_BUFF_FIFO_THRSLD is buffer FIFO threshold register.
 * 0x0200~0x027C are cache FIFO_0~FIFO_31 threshold configuration register
 */
#define PPE_CFG_RX_BUFF_FIFO_0_THRSLD_0_REG         (0x200)
/* PPE_CFG_RX_BUFF_FIFO_THRSLD is buffer FIFO threshold register.
 * 0x0200~0x027C are cache FIFO_0~FIFO_31 threshold configuration register
 */
#define PPE_CFG_RX_BUFF_FIFO_0_THRSLD_1_REG         (0x204)
/* PPE_CFG_POOL_GRP is 32 which GRP POOL can be allocated to use,0x0300~0x037C are POOL0~POOL31 configuration */
#define PPE_CFG_POOL_GRP_0_REG                      (0x300)
/* PPE_CFG_POOL_GRP is 32 which GRP POOL can be allocated to use,0x0300~0x037C are POOL0~POOL31 configuration */
#define PPE_CFG_POOL_GRP_1_REG                      (0x304)
/* PPE_CFG_RX_BUFF_FIFO_RX_BUF_SIZE is buffer FIFO buffer size configuration register.
 * FIFO_0~FIFO_31 the  0x0400~0x047C are cache size configuration register
 */
#define PPE_CFG_RX_BUFF_FIFO_RX_BUF_SIZE_0_REG      (0x400)
/* PPE_CFG_RX_BUFF_FIFO_RX_BUF_SIZE is buffer FIFO buffer size configuration register.
 * FIFO_0~FIFO_31 the  0x0400~0x047C are cache size configuration register
 */
#define PPE_CFG_RX_BUFF_FIFO_RX_BUF_SIZE_1_REG      (0x404)
/* PPE_CFG_RX_BUFF_FIFO_SIZE buffer FIFO size configuration register.
 * FIFO_0~FIFO_31 0x0500~0x057C are cache size configuration register
 */
#define PPE_CFG_RX_BUFF_FIFO_SIZE_0_REG             (0x500)
/* PPE_CFG_RX_BUFF_FIFO_SIZE buffer FIFO size configuration register.
 * FIFO_0~FIFO_31 0x0500~0x057C are cache size configuration register
 */
#define PPE_CFG_RX_BUFF_FIFO_SIZE_1_REG             (0x504)
/* PPE_CFG_TYPE_ITEM to QOS/GRP/VMID for various packets generated by type.
 * 0x2000~0x24FC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_0_REG                     (0x2000)
/* PPE_CFG_TYPE_ITEM to QOS/GRP/VMID for various packets generated by type.
 * 0x2000~0x24FC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_1_REG                     (0x2004)
/* PPE_CFG_TYPE_ITEM0_MSK is generated by type QOS/GRP/VMID mask configuration of various packets.
 * 0x2400~0x27FC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_MSK_0_REG                 (0x2400)
/* PPE_CFG_TYPE_ITEM0_MSK is generated by type QOS/GRP/VMID mask configuration of various packets.
 * 0x2400~0x27FC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_MSK_1_REG                 (0x2404)
/* PPE_CFG_TYPE_ITEM_QOS_MODE to QOS/GRP/VMID various packets generated by type mode 1.
 * 0x2800~0x2BFC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_QOS_MODE_0_REG            (0x2800)
/* PPE_CFG_TYPE_ITEM_QOS_MODE to QOS/GRP/VMID various packets generated by type mode 1.
 * 0x2800~0x2BFC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_QOS_MODE_1_REG            (0x2804)
/* PPE_CFG_TYPE_ITEM_QOS_OFFSET to QOS/GRP/VMID various packets generated by type mode 2.
 * 0x2C00~0x2CFC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_QOS_OFFSET_0_REG          (0x2C00)
/* PPE_CFG_TYPE_ITEM_QOS_OFFSET to QOS/GRP/VMID various packets generated by type mode 2.
 * 0x2C00~0x2CFC are paragraphs types 0~255 data packets
 */
#define PPE_CFG_TYPE_ITEM_QOS_OFFSET_1_REG          (0x2C04)
/* PPE_CFG_QOS_TBL0 is the zero table to generate QOS-0. */
#define PPE_CFG_QOS_TBL0_0_REG                      (0x4000)
/* PPE_CFG_QOS_TBL0 is the zero table to generate QOS-0. */
#define PPE_CFG_QOS_TBL0_1_REG                      (0x4004)
/* PPE_CFG_QOS_TBL1 is the 1st table to generate QOS-1. */
#define PPE_CFG_QOS_TBL1_0_REG                      (0x4020)
/* PPE_CFG_QOS_TBL1 is the 1st table to generate QOS-1. */
#define PPE_CFG_QOS_TBL1_1_REG                      (0x4024)
/* PPE_CFG_QOS_TBL2 is the 2nd table to generate QOS-2. */
#define PPE_CFG_QOS_TBL2_0_REG                      (0x4040)
/* PPE_CFG_QOS_TBL2 is the 2nd table to generate QOS-2. */
#define PPE_CFG_QOS_TBL2_1_REG                      (0x4044)
/* PPE_CFG_QOS_TBL3 is the 3rd table to generate QOS-3. */
#define PPE_CFG_QOS_TBL3_0_REG                      (0x4060)
/* PPE_CFG_QOS_TBL3 is the 3rd table to generate QOS-3. */
#define PPE_CFG_QOS_TBL3_1_REG                      (0x4064)
/* PPE_CFG_QOS_TBL4 is the 4th table to generate QOS-4. */
#define PPE_CFG_QOS_TBL4_0_REG                      (0x4080)
/* PPE_CFG_QOS_TBL4 is the 4th table to generate QOS-4. */
#define PPE_CFG_QOS_TBL4_1_REG                      (0x4084)
/* PPE_CFG_QOS_TBL5 is the 5th table to generate QOS-5. */
#define PPE_CFG_QOS_TBL5_0_REG                      (0x40A0)
/* PPE_CFG_QOS_TBL5 is the 5th table to generate QOS-5. */
#define PPE_CFG_QOS_TBL5_1_REG                      (0x40A4)
/* PPE_CFG_QOS_TBL6 is the 6th table to generate QOS-6. */
#define PPE_CFG_QOS_TBL6_0_REG                      (0x40C0)
/* PPE_CFG_QOS_TBL6 is the 6th table to generate QOS-6. */
#define PPE_CFG_QOS_TBL6_1_REG                      (0x40C4)
/* PPE_CFG_QOS_TBL7 is the 7th table to generate QOS-7. */
#define PPE_CFG_QOS_TBL7_0_REG                      (0x40E0)
/* PPE_CFG_QOS_TBL7 is the 7th table to generate QOS-7. */
#define PPE_CFG_QOS_TBL7_1_REG                      (0x40E4)
/* PPE_CFG_QOS_TBL0_KEY_EN is QOS table key generated configuration 1 register.
 * 0x4104~0x413C are 0~7 configuration tables
 */
#define PPE_CFG_QOS_TBL_KEY_EN_0_REG                (0x4104)
/* PPE_CFG_QOS_TBL0_KEY_EN is QOS table key generated configuration 1 register.
 * 0x4104~0x413C are 0~7 configuration tables
 */
#define PPE_CFG_QOS_TBL_KEY_EN_1_REG                (0x410C)
/* PPE_CFG_GRP_VMID_TBL0_KEY_OFFSET0 is to generate GRP and VMID table configuration register 0
 * of the key is generated. 0x5D00~0x5D50 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0_0_REG      (0x5D00)
/* PPE_CFG_GRP_VMID_TBL0_KEY_OFFSET0 is to generate GRP and VMID table configuration register 0
 * of the key is generated. 0x5D00~0x5D50 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0_1_REG      (0x5D08)
/* PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0 is to generate GRP and VMID table configuration register
 * 1 key is generated. 0x5D04~0x5D54 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET1_0_REG      (0x5D04)
/* PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0 is to generate GRP and VMID table configuration register
 * 1 key is generated. 0x5D04~0x5D54 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET1_1_REG      (0x5D0C)
/* PPE_CFG_GRP_TBL0 is the zero Query table  to generate GRP-0. */
#define PPE_CFG_GRP_TBL0_0_REG                      (0x5000)
/* PPE_CFG_GRP_TBL0 is the zero Query table  to generate GRP-0. */
#define PPE_CFG_GRP_TBL0_1_REG                      (0x5004)
/* PPE_CFG_GRP_TBL1 is the 1st Query table  to generate GRP-1. */
#define PPE_CFG_GRP_TBL1_0_REG                      (0x5100)
/* PPE_CFG_GRP_TBL1 is the 1st Query table  to generate GRP-1. */
#define PPE_CFG_GRP_TBL1_1_REG                      (0x5104)
/* PPE_CFG_GRP_TBL2 is the 2nd Query table  to generate GRP-2. */
#define PPE_CFG_GRP_TBL2_0_REG                      (0x5200)
/* PPE_CFG_GRP_TBL2 is the 2nd Query table  to generate GRP-2. */
#define PPE_CFG_GRP_TBL2_1_REG                      (0x5204)
/* PPE_CFG_GRP_TBL3 is the 3rd Query table  to generate GRP-3. */
#define PPE_CFG_GRP_TBL3_0_REG                      (0x5300)
/* PPE_CFG_GRP_TBL3 is the 3rd Query table  to generate GRP-3. */
#define PPE_CFG_GRP_TBL3_1_REG                      (0x5304)
/* PPE_CFG_GRP_TBL4 is the 4th Query table  to generate GRP-4. */
#define PPE_CFG_GRP_TBL4_0_REG                      (0x5400)
/* PPE_CFG_GRP_TBL4 is the 4th Query table  to generate GRP-4. */
#define PPE_CFG_GRP_TBL4_1_REG                      (0x5404)
/* PPE_CFG_GRP_TBL5 is the 5th Query table  to generate GRP-5. */
#define PPE_CFG_GRP_TBL5_0_REG                      (0x5500)
/* PPE_CFG_GRP_TBL5 is the 5th Query table  to generate GRP-5. */
#define PPE_CFG_GRP_TBL5_1_REG                      (0x5504)
/* PPE_CFG_GRP_TBL6 is the 6th Query table  to generate GRP-6. */
#define PPE_CFG_GRP_TBL6_0_REG                      (0x5600)
/* PPE_CFG_GRP_TBL6 is the 6th Query table  to generate GRP-6. */
#define PPE_CFG_GRP_TBL6_1_REG                      (0x5604)
/* PPE_CFG_GRP_TBL7 is the 7th Query table  to generate GRP-7. */
#define PPE_CFG_GRP_TBL7_0_REG                      (0x5700)
/* PPE_CFG_GRP_TBL7 is the 7th Query table  to generate GRP-7. */
#define PPE_CFG_GRP_TBL7_1_REG                      (0x5704)
/* PPE_CFG_GRP_TBL8 is the 8th Query table  to generate GRP-8. */
#define PPE_CFG_GRP_TBL8_0_REG                      (0x5800)
/* PPE_CFG_GRP_TBL8 is the 8th Query table  to generate GRP-8. */
#define PPE_CFG_GRP_TBL8_1_REG                      (0x5804)
/* PPE_CFG_GRP_TBL9 is the 9th Query table  to generate GRP-9. */
#define PPE_CFG_GRP_TBL9_0_REG                      (0x5900)
/* PPE_CFG_GRP_TBL9 is the 9th Query table  to generate GRP-9. */
#define PPE_CFG_GRP_TBL9_1_REG                      (0x5904)
/* PPE_CFG_GRP_TBL10 is the 10th Query table  to generate GRP-10. */
#define PPE_CFG_GRP_TBL10_0_REG                     (0x5A00)
/* PPE_CFG_GRP_TBL10 is the 10th Query table  to generate GRP-10. */
#define PPE_CFG_GRP_TBL10_1_REG                     (0x5A04)
/* PPE_CFG_GRP_CMP_TBL_VALUE are to generate GRP GRP value */
#define PPE_CFG_GRP_CMP_TBL_VALUE_0_REG             (0x5B00)
/* PPE_CFG_GRP_CMP_TBL_VALUE are to generate GRP GRP value */
#define PPE_CFG_GRP_CMP_TBL_VALUE_1_REG             (0x5B04)
/* PPE_CFG_GRP_CMP_TBL_VALUE are to generate GRP GRP value */
#define PPE_CFG_GRP_CMP_TBL_VALUE_2_REG             (0x5B20)
/* PPE_CFG_GRP_CMP_TBL_VALUE are to generate GRP GRP value */
#define PPE_CFG_GRP_CMP_TBL_VALUE_3_REG             (0x5B24)
/* PPE_CFG_VMID_TBL0 is the zero table to generate vmid-0. */
#define PPE_CFG_VMID_TBL0_0_REG                     (0x6000)
/* PPE_CFG_VMID_TBL0 is the zero table to generate vmid-0. */
#define PPE_CFG_VMID_TBL0_1_REG                     (0x6004)
/* PPE_CFG_VMID_TBL1 is the 1st table to generate vmid. */
#define PPE_CFG_VMID_TBL1_0_REG                     (0x6080)
/* PPE_CFG_VMID_TBL1 is the 1st table to generate vmid. */
#define PPE_CFG_VMID_TBL1_1_REG                     (0x6084)
/* PPE_CFG_VMID_TBL2 is the 2nd table to generate vmid. */
#define PPE_CFG_VMID_TBL2_0_REG                     (0x6100)
/* PPE_CFG_VMID_TBL2 is the 2nd table to generate vmid. */
#define PPE_CFG_VMID_TBL2_1_REG                     (0x6104)
/* PPE_CFG_VMID_TBL3 is the 3rd table to generate vmid. */
#define PPE_CFG_VMID_TBL3_0_REG                     (0x6180)
/* PPE_CFG_VMID_TBL3 is the 3rd table to generate vmid. */
#define PPE_CFG_VMID_TBL3_1_REG                     (0x6184)
/* PPE_CFG_VMID_TBL4 is the 4th table to generate vmid. */
#define PPE_CFG_VMID_TBL4_0_REG                     (0x6200)
/* PPE_CFG_VMID_TBL4 is the 4th table to generate vmid. */
#define PPE_CFG_VMID_TBL4_1_REG                     (0x6204)
/* PPE_CFG_VMID_TBL5 is the 5th table to generate vmid. */
#define PPE_CFG_VMID_TBL5_0_REG                     (0x6280)
/* PPE_CFG_VMID_TBL5 is the 5th table to generate vmid. */
#define PPE_CFG_VMID_TBL5_1_REG                     (0x6284)
/* PPE_CFG_VMID_TBL6 is the 6th table to generate vmid. */
#define PPE_CFG_VMID_TBL6_0_REG                     (0x6300)
/* PPE_CFG_VMID_TBL6 is the 6th table to generate vmid. */
#define PPE_CFG_VMID_TBL6_1_REG                     (0x6304)
/* PPE_CFG_VMID_TBL7 is the 7th table to generate vmid. */
#define PPE_CFG_VMID_TBL7_0_REG                     (0x6380)
/* PPE_CFG_VMID_TBL7 is the 7th table to generate vmid. */
#define PPE_CFG_VMID_TBL7_1_REG                     (0x6384)
/* PPE_CFG_VMID_TBL8 is the 8th table to generate vmid. */
#define PPE_CFG_VMID_TBL8_0_REG                     (0x6400)
/* PPE_CFG_VMID_TBL8 is the 8th table to generate vmid. */
#define PPE_CFG_VMID_TBL8_1_REG                     (0x6404)
/* PPE_CFG_VMID_TBL9 is the 9th table to generate vmid. */
#define PPE_CFG_VMID_TBL9_0_REG                     (0x6480)
/* PPE_CFG_VMID_TBL9 is the 9th table to generate vmid. */
#define PPE_CFG_VMID_TBL9_1_REG                     (0x6484)
/* PPE_CFG_VMID_TBL0 is the 10th table to generate vmid. */
#define PPE_CFG_VMID_TBL10_0_REG                    (0x6500)
/* PPE_CFG_VMID_TBL0 is the 10th table to generate vmid. */
#define PPE_CFG_VMID_TBL10_1_REG                    (0x6504)
/* PPE_CFG_VMID_CMP_TBL_VALUE are Generating VMID VMID value */
#define PPE_CFG_VMID_CMP_TBL_VALUE_0_REG            (0x6580)
/* PPE_CFG_VMID_CMP_TBL_VALUE are Generating VMID VMID value */
#define PPE_CFG_VMID_CMP_TBL_VALUE_1_REG            (0x6584)
/* PPE_CFG_VMID_CMP_TBL_VALUE are Generating VMID VMID value */
#define PPE_CFG_VMID_CMP_TBL_VALUE_2_REG            (0x6590)
/* PPE_CFG_VMID_CMP_TBL_VALUE are Generating VMID VMID value */
#define PPE_CFG_VMID_CMP_TBL_VALUE_3_REG            (0x6594)
/* PPE_CFG_GRP_VMID_CMP_TBL0 is the zero table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL0_0_REG             (0x7000)
/* PPE_CFG_GRP_VMID_CMP_TBL1 is the 1st table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL1_0_REG             (0x7100)
/* PPE_CFG_GRP_VMID_CMP_TBL2 is the 2nd table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL2_0_REG             (0x7200)
/* PPE_CFG_GRP_VMID_CMP_TBL3 is the 3rd table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL3_0_REG             (0x7300)
/* PPE_CFG_GRP_VMID_CMP_TBL0_MSK is the mask value of the zero table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL0_MSK_0_REG         (0x7B00)
/* PPE_CFG_GRP_VMID_CMP_TBL1_MSK is the mask value of the 1st table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL1_MSK_0_REG         (0x7B08)
/* PPE_CFG_GRP_VMID_CMP_TBL2_MSK is the mask value of the 2nd table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL2_MSK_0_REG         (0x7B10)
/* PPE_CFG_GRP_VMID_CMP_TBL3_MSK is the mask value of the 3rd table to generate GRP_VMID. */
#define PPE_CFG_GRP_VMID_CMP_TBL3_MSK_0_REG         (0x7B18)
/* PPE_INTEN_0 is 0 interrupt enable register. */
#define PPE_INTEN_0_REG                             (0x8000)
/* PPE_RINT_0 0 is the raw interrupt register. */
#define PPE_RINT_0_REG                              (0x8004)
/* PPE_INTSTS_0 is 0 interrupt status register. */
#define PPE_INTSTS_0_REG                            (0x8008)
/* PPE_INTEN_1 is 1 interrupt enable register. */
#define PPE_INTEN_1_REG                             (0x8010)
/* PPE_RINT_1 1 is the raw interrupt register. */
#define PPE_RINT_1_REG                              (0x8014)
/* PPE_INTSTS_1 is 1 interrupt status register. */
#define PPE_INTSTS_1_REG                            (0x8018)
/* PPE_RINT_2 is the interrupt enable register 2. */
#define PPE_INTEN_2_REG                             (0x8020)
/* PPE_RINT_2 2 is the raw interrupt register. */
#define PPE_RINT_2_REG                              (0x8024)
/* 2 PPE_INTSTS_2 is the interrupt status register. */
#define PPE_INTSTS_2_REG                            (0x8028)
/* PPE_CFG_STS_MODE_0 is register attribute is 0 CNT_CYC read enable register. */
#define PPE_CFG_STS_MODE_0_REG                      (0xA000)
/* PPE_CFG_STS_MODE_1 is register attribute is 1 CNT_CYC read enable register. */
#define PPE_CFG_STS_MODE_1_REG                      (0xA004)
/* PPE_HIS_PKT_GRP_CN is received packets according to the statistics.  GRP */
#define PPE_HIS_PKT_GRP_CNT_0_REG                   (0xA100)
/* PPE_HIS_PKT_GRP_CN is received packets according to the statistics.  GRP */
#define PPE_HIS_PKT_GRP_CNT_1_REG                   (0xA104)
/* PPE_HIS_PKT_QOS_CN is received packets by QOS statistics. */
#define PPE_HIS_PKT_QOS_CNT_0_REG                   (0xA180)
/* PPE_HIS_PKT_QOS_CN is received packets by QOS statistics. */
#define PPE_HIS_PKT_QOS_CNT_1_REG                   (0xA184)
/* PPE_HIS_DROP_PKT_QOS_CNT are discarded packets based on the QOS statistics. */
#define PPE_HIS_DROP_PKT_QOS_CNT_0_REG              (0xA1A0)
/* PPE_HIS_DROP_PKT_QOS_CNT are discarded packets based on the QOS statistics. */
#define PPE_HIS_DROP_PKT_QOS_CNT_1_REG              (0xA1A4)
/* PPE_HIS_MST_WR_CNT is MASTER write operation statistics. */
#define PPE_HIS_MST_WR_CNT_0_REG                    (0xA1C0)
/* PPE_HIS_MST_WR_CNT is MASTER write operation statistics. */
#define PPE_HIS_MST_WR_CNT_1_REG                    (0xA1C4)
/* PPE_HIS_MST_RD_CNT is MASTER write operation statistics. */
#define PPE_HIS_MST_RD_CNT_0_REG                    (0xA1D8)
/* PPE_HIS_MST_RD_CNT is MASTER write operation statistics. */
#define PPE_HIS_MST_RD_CNT_1_REG                    (0xA1DC)
/* BMU PPE_HIS_REQ_BMU_FAIL_CNT is application failure statistics. */
#define PPE_HIS_REQ_BMU_FAIL_CNT_REG                (0xA1F0)
/* PPE_HIS_REQ_BMU_OK_CNT application BMU is statistics. */
#define PPE_HIS_REQ_BMU_OK_CNT_REG                  (0xA1F4)
/* PPE_CURR_BUF_CNT. 0xA200~0xA27C are the number of cached pool_0~pool_31 buffer pointer */
#define PPE_CURR_BUF_CNT_0_REG                      (0xA200)
/* PPE_CURR_BUF_CNT. 0xA200~0xA27C are the number of cached pool_0~pool_31 buffer pointer */
#define PPE_CURR_BUF_CNT_1_REG                      (0xA204)
/* PPE_CURR_CAN_RST is whether the channel can be reset. */
#define PPE_CURR_CMM_CAN_RST_REG                    (0xA300)
/* Internal FIFO overflow.  PPE_HIS_FIFO_ERR is */
#define PPE_HIS_FIFO_ERR_REG                        (0xA304)
/* PPE_CURR_FIFO_0 is BMU return data FIFO status. */
#define PPE_CURR_FIFO_0_REG                         (0xA308)
/* PPE_CURR_FIFO_0 for BMU command FIFO status. */
#define PPE_CURR_FIFO_1_REG                         (0xA30C)
/* PPE_HIS_MST_RD_LAT is MASTER read delay statistics. */
#define PPE_HIS_MST_RD_LAT_0_REG                    (0xA310)
/* PPE_HIS_MST_RD_LAT is MASTER read delay statistics. */
#define PPE_HIS_MST_RD_LAT_1_REG                    (0xA314)
/* PPE_HIS_MST_WR_LAT is MASTER write delay statistics. */
#define PPE_HIS_MST_WR_LAT_0_REG                    (0xA328)
/* PPE_HIS_MST_WR_LAT is MASTER write delay statistics. */
#define PPE_HIS_MST_WR_LAT_1_REG                    (0xA32C)
/* PPE_HIS_MST_RD_STS_1 MASTER read operation is 1. */
#define PPE_HIS_MST_RD_STS_1_0_REG                  (0xA340)
/* PPE_HIS_MST_RD_STS_1 MASTER read operation is 1. */
#define PPE_HIS_MST_RD_STS_1_1_REG                  (0xA344)
/* PPE_HIS_MST_RD_STS_2 MASTER read operation is 2. */
#define PPE_HIS_MST_RD_STS_2_0_REG                  (0xA358)
/* PPE_HIS_MST_RD_STS_2 MASTER read operation is 2. */
#define PPE_HIS_MST_RD_STS_2_1_REG                  (0xA35C)
/* PPE_HIS_MST_RD_STS_1 write operation status is MASTER. */
#define PPE_HIS_MST_WR_STS_1_0_REG                  (0xA370)
/* PPE_HIS_MST_RD_STS_1 write operation status is MASTER. */
#define PPE_HIS_MST_WR_STS_1_1_REG                  (0xA374)
/* PPE_HIS_MST_RD_STS_2 write operation status is MASTER. */
#define PPE_HIS_MST_WR_STS_2_0_REG                  (0xA388)
/* PPE_HIS_MST_RD_STS_2 write operation status is MASTER. */
#define PPE_HIS_MST_WR_STS_2_1_REG                  (0xA38C)
/* PPE_HIS_MST_RD_STS_3 write operation status is MASTER. */
#define PPE_HIS_MST_WR_STS_3_0_REG                  (0xA3A0)
/* PPE_HIS_MST_RD_STS_3 write operation status is MASTER. */
#define PPE_HIS_MST_WR_STS_3_1_REG                  (0xA3A4)
/* PPE_HIS_MST_RD_STS_3 write operation status is MASTER. */
#define PPE_HIS_MST_RD_STS_3_0_REG                  (0xA3B8)
/* PPE_HIS_MST_RD_STS_3 write operation status is MASTER. */
#define PPE_HIS_MST_RD_STS_3_1_REG                  (0xA3BC)
/* PPE_CFG_MST_STS_CLR is MASTER statistics clear register. */
#define PPE_CFG_MST_STS_CLR_0_REG                   (0xA3D0)
/* PPE_CFG_MST_STS_CLR is MASTER statistics clear register. */
#define PPE_CFG_MST_STS_CLR_1_REG                   (0xA3D4)
/* PPE_CFG_OAM_TX_TIEM is Y.1731 Tx traffic matching statistics. */
#define PPE_CFG_OAM_TX_ITEM_STS_0_REG               (0xB000)
/* PPE_CFG_OAM_TX_TIEM is Y.1731 Tx traffic matching statistics. */
#define PPE_CFG_OAM_TX_ITEM_STS_1_REG               (0xB004)
/* Time synchronization second high configuration register. */
#define PPE_CFG_TIME_SYNC_H_REG                     (0xC000)
/* Time synchronization second low configuration register. */
#define PPE_CFG_TIME_SYNC_M_REG                     (0xC004)
/* Time synchronization Nano-second configuration register. */
#define PPE_CFG_TIME_SYNC_L_REG                     (0xC008)
/* Time synchronization enable configuration register. */
#define PPE_CFG_TIME_SYNC_RDY_REG                   (0xC00C)
/* Time synchronization offset enable configuration register. */
#define PPE_CFG_PTP_OFFSET_ADD_RDY_REG              (0xC010)
/* RTC timing clock period Nano-second integer value register. */
#define PPE_CFG_TIME_CYC_NS_REG                     (0xC014)
/* RTC timing clock period Nano-second decimal value register. */
#define PPE_CFG_TIME_CYC_NS_DEC_REG                 (0xC018)
/* The system clock period configuration register. */
#define PPE_CFG_SYS_CYC_REG                         (0xC01C)
/* 1PPS interrupt enable register. */
#define PPE_CFG_INT_1PPS_EN_REG                     (0xC020)
/* 1PPS interrupt clear register. */
#define PPE_CFG_INTS_1PPS_CLR_REG                   (0xC024)
/* 1PPS interrupt status register. */
#define PPE_CFG_INTS_1PPS_REG                       (0xC028)
/* Local time (s) high output register. */
#define PPE_CURR_TIME_OUT_H_REG                     (0xC02C)
/* Local time second low output register. */
#define PPE_CURR_TIME_OUT_L_REG                     (0xC030)
/* Nano-second output register local time. */
#define PPE_CURR_TIME_OUT_NS_REG                    (0xC034)
/* The local timing clock selection register */
#define PPE_CFG_TS_CLK_SEL_REG                      (0xC038)
/* The system clock sampling time compensation offset configuration register. */
#define PPE_CFG_SYS_TIME_OFFSET_REG                 (0xC03C)

/* P650 PPE_TNL_0_11 register defined
 * PPE_CFG_TX_FIFO_THRSLD is the TX FIFO threshold register.
 */
#define PPE_CFG_TX_FIFO_THRSLD_REG                  (0x400)
/* PPE_CFG_RX_FIFO_THRSLD is the RX FIFO threshold register. */
#define PPE_CFG_RX_FIFO_THRSLD_REG                  (0x404)
/* Overlong MAX_FRAME_LEN to receive frame threshold register. */
#define PPE_CFG_MAX_FRAME_LEN_REG                   (0x500)
/* PPE_CFG_TX_PAUSE is a TX control register. */
#define PPE_CFG_TX_PAUSE_REG                        (0x40C)
/* Traffic control PPE_CFG_RX_FIFO_PAUSE_THRSLD is the RX FIFO threshold register. */
#define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG            (0x410)
/* PPE_CFG_RX_FIFO_BUS_THRSLD is the RX FIFO backpressure bus threshold register. */
#define PPE_CFG_RX_FIFO_BUS_THRSLD_REG              (0x414)
/* PPE_CFG_TX_BD_ADDR_THRSLD is a descriptor address FIFO threshold register. */
#define PPE_CFG_TX_BD_ADDR_THRSLD_REG               (0x418)
/* Configure the PPE_CFG_XGE_MODE channel is connected to the GE or XGE */
#define PPE_CFG_XGE_MODE_REG                        (0x41C)
/* PPE_CFG_TX_PKT_BUF_ADDR is a descriptor address. */
#define PPE_CFG_TX_PKT_BD_ADDR_REG                  (0x6D0)
/* PPE_CFG_BUS_CTRL is bus control register */
#define PPE_CFG_BUS_CTRL_REG                        (0x424)
/* PPE_CFG_RX_CTRL is an RX control register. */
#define PPE_CFG_RX_CTRL_REG                         (0x428)
/* PPE_CFG_RX_PD_TIMER workentry fails to receive write timeout register. */
#define PPE_CFG_RX_WE_TIMER_REG                     (0x42C)
/* BMU configuration register.  PPE_CFG_REL_BMU_TIMER is released */
#define PPE_CFG_REL_BMU_TIMER_REG                   (0x430)
/* PPE_CFG_PAUSE_IDLE_CNT is control register  PAUSE frames sent */
#define PPE_CFG_PAUSE_IDLE_CNT_REG                  (0x434)
/* PPE_CFG_RX_PKT_MODE input mode.  to receive packets */
#define PPE_CFG_RX_PKT_MODE_REG                     (0x504)
/* PPE_CFG_RX_VLAN_TAG is receiving packets 2 VLAN outer tag value */
#define PPE_CFG_RX_VLAN_TAG_REG                     (0x43C)
/* PPE_CFG_TX_DECT_EN is sent 1588DECT enable */
#define PPE_CFG_TX_DECT_EN_REG                      (0x440)
/* DECT detection sending VLAN TAG configuration register. */
#define PPE_CFG_TX_VLAN_TAG_REG                     (0x444)
/* DECT detection PTP packets sent UDP destination port number configuration register. */
#define PPE_CFG_TX_PTP_DPN_REG                      (0x448)
/* PPE_CFG_QOS_GRP_VMID_GEN is QOS, GRP, VMID generation mode register. */
#define PPE_CFG_QOS_GRP_VMID_GEN_REG                (0x520)
/* PPE_CFG_TAG_TT_GEN indicates the TAG, TT generation mode register */
#define PPE_CFG_TNL_TO_BE_RST                       (0x4F8)
#define PPE_CURR_TNL_CAN_RST                        (0x4FC)
/* PPE_CFG_PARSE_TAG is parsing mode, each NE mask configuration register */
#define PPE_CFG_PARSE_TAG_REG                       (0x508)
/* PPE_CFG_TAG_OFFSET mask mode for calculating tag is
 * optional 128-byte packet offset register configuration
 */
#define PPE_CFG_TAG_OFFSET_REG                      (0x50C)
/* PPE_CFG_TAG_BIT_MASK1 mask mode for calculating tag is
 * optional 128-byte packets Byte 0~31 mask configuration register.
 */
#define PPE_CFG_TAG_BYTE_MASK1_REG                  (0x510)
/* PPE_CFG_TAG_BIT_MASK2 mask mode for calculating tag is
 * optional 128-byte packets 32~63 bytes mask configuration register.
 */
#define PPE_CFG_TAG_BYTE_MASK2_REG                  (0x514)
/* PPE_CFG_TAG_BIT_MASK3 mask mode for calculating tag is
 * optional 128 packets in 64~95 bytes mask configuration register.
 */
#define PPE_CFG_TAG_BYTE_MASK3_REG                  (0x518)
/* PPE_CFG_TAG_BIT_MASK3 mask mode for calculating tag is
 * optional 128 packets 96~127 bytes mask configuration register.
 */
#define PPE_CFG_TAG_BYTE_MASK4_REG                  (0x51C)
/* PPE_CFG_TAG_BIT_MASK mask mode for calculating tag
 * is optional in the 128-byte packets 2 byte bitwise mask configuration register.
 */
#define PPE_CFG_TAG_BIT_MASK_REG                    (0x524)
/* PPE_CFG_AR_TAG1_CFG special VLAN_ID is AR generates a TAG. */
#define PPE_CFG_AR_TAG1_CFG_REG                     (0x528)
/* PPE_CFG_AR_TAG1_CFG is AR specified types of packets generated TAG. */
#define PPE_CFG_AR_TAG2_CFG_REG                     (0x52C)
/* PPE_CFG_AR_SPE_CFG is AR 2 specified TAG. */
#define PPE_CFG_AR_SPE_CFG_REG                      (0x530)
/* Checking PPE_CFG_PRO_CHECK_EN is enabled. */
#define PPE_CFG_PRO_CHECK_EN_REG                    (0x534)
/* PPE_CFG_RX_PKT_INT is received from a specified number
 * or receive packets timeout interrupt is reported.
 */
#define PPE_CFG_RX_PKT_INT_REG                      (0x740)
/* 704 */
#define PPE_CFG_HEAT_DECT_TIME0_REG                 (0x53C)
/* PPE_CFG_HEAT_DECT_TIME1 is state machine heartbeat detection timeout
 * register configuration register 1
 */
#define PPE_CFG_HEAT_DECT_TIME1_REG                 (0x540)
/* PPE_CFG_TO_BE_RST is the channel is to be reset. */
#define PPE_CFG_TO_BE_RST_REG                       (0x544)
/* PPE_CFG_DELAY_CLR is read/write DDR max time delay. */
#define PPE_CFG_DELAY_CLR_REG                       (0x548)
/* PPE_CFG_CPU_ADD_ADDR is 16 CPU push transmit descriptor,0x0580~0x05BC are CPU0~CPU15 push address */
#define PPE_CFG_CPU_ADD_ADDR_0_REG                  (0x580)
/* PPE_CFG_CPU_ADD_ADDR is 16 CPU push transmit descriptor,0x0580~0x05BC are CPU0~CPU15 push address */
#define PPE_CFG_CPU_ADD_ADDR_1_REG                  (0x584)
/* PPE_CFG_CPU_ADD_ADDR_FAIL0 is CPU0 push Transmit Descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL0_REG              (0x5C0)
/* PPE_CFG_CPU_ADD_ADDR_FAIL1 CPU1 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL1_REG              (0x5C4)
/* PPE_CFG_CPU_ADD_ADDR_FAIL2 CPU2 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL2_REG              (0x5C8)
/* PPE_CFG_CPU_ADD_ADDR_FAIL3 CPU3 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL3_REG              (0x5CC)
/* PPE_CFG_CPU_ADD_ADDR_FAIL4 CPU4 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL4_REG              (0x5D0)
/* PPE_CFG_CPU_ADD_ADDR_FAIL5 CPU5 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL5_REG              (0x5D4)
/* PPE_CFG_CPU_ADD_ADDR_FAIL6 is sent CPU6 push descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL6_REG              (0x5D8)
/* PPE_CFG_CPU_ADD_ADDR_FAIL7 CPU7 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL7_REG              (0x5DC)
/* PPE_CFG_CPU_ADD_ADDR_FAIL8 is sent CPU8 push descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL8_REG              (0x5E0)
/* PPE_CFG_CPU_ADD_ADDR_FAIL9 CPU9 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL9_REG              (0x5E4)
/* PPE_CFG_CPU_ADD_ADDR_FAIL10 CPU10 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL10_REG             (0x5E8)
/* PPE_CFG_CPU_ADD_ADDR_FAIL11 CPU11 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL11_REG             (0x5EC)
/* PPE_CFG_CPU_ADD_ADDR_FAIL12 CPU12 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL12_REG             (0x5F0)
/* PPE_CFG_CPU_ADD_ADDR_FAIL13 CPU13 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL13_REG             (0x5F4)
/* PPE_CFG_CPU_ADD_ADDR_FAIL14 CPU14 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL14_REG             (0x5F8)
/* PPE_CFG_CPU_ADD_ADDR_FAIL15 CPU15 push sends a descriptor failure indication */
#define PPE_CFG_CPU_ADD_ADDR_FAIL15_REG             (0x5FC)
/* PPE_INTEN is the interrupt enable register. */
#define PPE_INTEN_REG                               (0x700)
/* PPE_RINT is the raw interrupt register. */
#define PPE_RINT_REG                                (0x704)
/* PPE_INTSTS is the interrupt status register. */
#define PPE_INTSTS_REG                              (0x708)
/* PPE_INT_VMID VMID register will be interrupted. */
#define PPE_INT_VMID_REG                            (0x60C)
/* PPE_CFG_AXI_DBG is AXIDEBUG register. */
#define PPE_CFG_AXI_DBG_REG                         (0x610)
/* PPE_HIS_RX_PKT_OK_CNT is successfully received and
 * the packet statistics of the POE is added successfully.
 */
#define PPE_HIS_RX_PKT_OK_CNT_REG                   (0x704)
/* PPE_HIS_RX_PKT_DROP_FUL_CNT is due to full FIFO entire packet discarding statistics. */
#define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG             (0x708)
/* PPE_HIS_RX_PKT_DROP_PRT_CNT is truncated due to full FIFO packets statistics. */
#define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG             (0x70C)
/* PPE_HIS_RX_PKT_LOW_QOS_CNT is due to insufficient QOS discarded packet statistics. */
#define PPE_HIS_RX_PKT_LOW_QOS_CNT_REG              (0x710)
/* PPE_HIS_RX_PKT_NO_BUF_CNT is discarded because no corresponding BUF and receive FIFO packets. */
#define PPE_HIS_RX_PKT_NO_BUF_CNT_REG               (0x714)
/* PPE_HIS_TX_PKT_OK_CNT are successfully sent packet statistics. */
#define PPE_HIS_TX_PKT_OK_CNT_REG                   (0x718)
/* TX FIFO empty PPE_HIS_TX_PKT_EPT_CNT is truncated packets. */
#define PPE_HIS_TX_PKT_EPT_CNT_REG                  (0x71C)
/* PPE_HIS_TX_PKT_CS_FAIL_CNT a checksum calculation failure packet statistics. */
#define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG              (0x720)
/* PPE_HIS_REL_BUF_FAIL_CNT a Failed to release the cache statistics. */
#define PPE_HIS_REL_BUF_FAIL_CNT_REG                (0x724)
/* PPE_HIS_RX_ADD_POE_TM_BMU_FAIL_CNT is received write POE/TM/BMU failure statistics. */
#define PPE_HIS_RX_ADD_POE_TM_BMU_FAIL_CNT_REG      (0x728)
/* PPE_HIS_RX_ADD_TM_BMU_OK_CNTT is successfully received write TM/BMU statistics. */
#define PPE_HIS_RX_ADD_TM_BMU_OK_CNT_REG            (0x72C)
/* PPE_CURR_DATA_NUM is the configuration FIFO data count register. */
#define PPE_CURR_CFF_DATA_NUM_REG                   (0x8C8)
/* PPE_CURR_CAN_RST is whether the channel can be reset. */
#define PPE_CURR_CAN_RST_REG                        (0x734)
/* PPE_HIS_PRO_ERR check once to a protocol error. */
#define PPE_HIS_PRO_ERR_REG                         (0x738)
/* Internal FIFO overflow.  PPE_HIS_FIFO_ERR is */
#define PPE_HIS_TNL_FIFO_ERR                        (0x73C)
/* PPE_CURR_TX_ST is the receive state machine status. */
#define PPE_CURR_TX_ST_REG                          (0x744)
/* 0 PPE_CURR_RX_FIFO0 is the RX FIFO status. */
#define PPE_CURR_RX_FIFO0_REG                       (0x748)
/* 1 PPE_CURR_RX_FIFO1 is the RX FIFO status. */
#define PPE_CURR_RX_FIFO1_REG                       (0x74C)
/* PPE_CURR_TX_FIFO0 is a TX FIFO status 0. */
#define PPE_CURR_TX_FIFO0_REG                       (0x750)
/* PPE_CURR_TX_FIFO1 is a TX FIFO status 1. */
#define PPE_CURR_TX_FIFO1_REG                       (0x754)
/* PPE_CURR_DDR_DELAY is read/write DDR max time delay. */
#define PPE_CURR_DDR_DELAY_REG                      (0x758)
/* PPE_ECO0 is eco 0 register. */
#define PPE_ECO0_REG                                (0x75C)
/* PPE_ECO1 is eco 1 register. */
#define PPE_ECO1_REG                                (0x760)
/* PPE_ECO2 is eco 2 register. */
#define PPE_ECO2_REG                                (0x764)
/* PPE_HIS_RX_MAC_PKT_CNT on the received MAC packets. */
#define PPE_HIS_RX_MAC_PKT_CNT_REG                  (0x800)
/* PPE_HIS_RX_WR_BD_OK_PKT_CNT is successfully written to the RX descriptor packets number. */
#define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG             (0x804)
/* PPE_HIS_TX_BD_ADDR_WR_CNT is written to the TX descriptor addresses. */
#define PPE_HIS_TX_BD_ADDR_WR_CNT_REG               (0x808)
/* PPE_HIS_RX_REL_BUF_CNT is Number of received release buffers. */
#define PPE_HIS_RX_REL_BUF_CNT_REG                  (0x80C)
/* Number of PPE_HIS_TX_REL_BUF_CNT a release the cache. */
#define PPE_HIS_TX_REL_BUF_CNT_REG                  (0x810)
/* PPE_CFG_L3_TYPE_VALUE_0 is the 0 value  Layer 3 types */
#define PPE_CFG_L3_TYPE_VALUE_0_REG                 (0x1000)
/* PPE_CFG_L3_TYPE_VALUE is the 0 value of MASK Layer 3 types */
#define PPE_CFG_L3_TYPE_MASK_0_REG                  (0x1004)
/* PPE_CFG_L3_TYPE_VALUE is the 0 protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_0_REG                (0x1008)
/* PPE_CFG_L3_TYPE_VALUE_1 is the 1 value  Layer 3 types */
#define PPE_CFG_L3_TYPE_VALUE_1_REG                 (0x1010)
/* PPE_CFG_L3_TYPE_VALUE to Layer 1 of 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_1_REG                  (0x1014)
/* PPE_CFG_L3_TYPE_VALUE is-1 protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_1_REG                (0x1018)
/* PPE_CFG_L3_TYPE_VALUE_2 is the value 2 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_2_REG                 (0x1020)
/* PPE_CFG_L3_TYPE_VALUE is Layer 2 types of 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_2_REG                  (0x1024)
/* PPE_CFG_L3_TYPE_VALUE is-2 protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_2_REG                (0x1028)
/* PPE_CFG_L3_TYPE_VALUE_3 is the 3 types of layer 3 value */
#define PPE_CFG_L3_TYPE_VALUE_3_REG                 (0x1030)
/* PPE_CFG_L3_TYPE_VALUE is Layer 3 types of 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_3_REG                  (0x1034)
/* Article 3 is PPE_CFG_L3_TYPE_VALUE protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_3_REG                (0x1038)
/* PPE_CFG_L3_TYPE_VALUE_4 is the value 4 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_4_REG                 (0x1040)
/* PPE_CFG_L3_TYPE_VALUE is Layer 4 types of 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_4_REG                  (0x1044)
/* PPE_CFG_L3_TYPE_VALUE is the 4 types of Layer 3 header protocol domain offset */
#define PPE_CFG_L3_TYPE_OFFSET_4_REG                (0x1048)
/* PPE_CFG_L3_TYPE_VALUE_5 is the value 5 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_5_REG                 (0x1050)
/* PPE_CFG_L3_TYPE_VALUE is the value 5 types of Layer 3 MASK */
#define PPE_CFG_L3_TYPE_MASK_5_REG                  (0x1054)
/* PPE_CFG_L3_TYPE_VALUE is-5 protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_5_REG                (0x1058)
/* PPE_CFG_L3_TYPE_VALUE_6 is the value 6 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_6_REG                 (0x1060)
/* PPE_CFG_L3_TYPE_VALUE is the value 6 types of Layer 3 MASK */
#define PPE_CFG_L3_TYPE_MASK_6_REG                  (0x1064)
/* PPE_CFG_L3_TYPE_VALUE to No. 7 protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_6_REG                (0x1068)
/* PPE_CFG_L3_TYPE_VALUE_7 is the value 7 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_7_REG                 (0x1070)
/* PPE_CFG_L3_TYPE_VALUE to No. 7 types of Layer 3 configuration value MASK */
#define PPE_CFG_L3_TYPE_MASK_7_REG                  (0x1074)
/* PPE_CFG_L3_TYPE_VALUE is the 8 types of Layer 3 header protocol field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_7_REG                (0x1078)
/* PPE_CFG_L3_TYPE_VALUE_8 is the value 8 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_8_REG                 (0x1080)
/* PPE_CFG_L3_TYPE_VALUE is the value 8 types of Layer 3 MASK */
#define PPE_CFG_L3_TYPE_MASK_8_REG                  (0x1084)
/* Article 9 is PPE_CFG_L3_TYPE_VALUE protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_8_REG                (0x1088)
/* PPE_CFG_L3_TYPE_VALUE_9 to Article 9 types of layer 3 value */
#define PPE_CFG_L3_TYPE_VALUE_9_REG                 (0x1090)
/* PPE_CFG_L3_TYPE_VALUE to Article 9 types of layer 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_9_REG                  (0x1094)
/* Article 9 is PPE_CFG_L3_TYPE_VALUE protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_9_REG                (0x1098)
/* PPE_CFG_L3_TYPE_VALUE_10 is the value 10 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_10_REG                (0x10A0)
/* PPE_CFG_L3_TYPE_VALUE to Article 10 types of Layer 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_10_REG                 (0x10A4)
/* PPE_CFG_L3_TYPE_VALUE to Article 10 types of Layer 3 header protocol field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_10_REG               (0x10A8)
/* PPE_CFG_L3_TYPE_VALUE_11 is the 1 value  Layer 3 types */
#define PPE_CFG_L3_TYPE_VALUE_11_REG                (0x10B0)
/* PPE_CFG_L3_TYPE_VALUE to No. 11 types of Layer 3 configuration value MASK */
#define PPE_CFG_L3_TYPE_MASK_11_REG                 (0x10B4)
/* PPE_CFG_L3_TYPE_VALUE to Article 11 types of Layer 3 header protocol domain offset */
#define PPE_CFG_L3_TYPE_OFFSET_11_REG               (0x10B8)
/* PPE_CFG_L3_TYPE_VALUE_12 is the value 12 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_12_REG                (0x10C0)
/* PPE_CFG_L3_TYPE_VALUE to No. 12 types of Layer 3 configuration value MASK */
#define PPE_CFG_L3_TYPE_MASK_12_REG                 (0x10C4)
/* PPE_CFG_L3_TYPE_VALUE is-12 types of Layer 3 header protocol field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_12_REG               (0x10C8)
/* PPE_CFG_L3_TYPE_VALUE_13 is the value 13 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_13_REG                (0x10D0)
/* PPE_CFG_L3_TYPE_VALUE to Article 13 types of layer 3 value MASK */
#define PPE_CFG_L3_TYPE_MASK_13_REG                 (0x10D4)
/* Article 13 is PPE_CFG_L3_TYPE_VALUE protocol types of Layer 3 header field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_13_REG               (0x10D8)
/* PPE_CFG_L3_TYPE_VALUE_14 is the value 14 types of Layer 3 */
#define PPE_CFG_L3_TYPE_VALUE_14_REG                (0x10E0)
/* PPE_CFG_L3_TYPE_VALUE is the value 14 types of Layer 3 MASK */
#define PPE_CFG_L3_TYPE_MASK_14_REG                 (0x10E4)
/* PPE_CFG_L3_TYPE_VALUE to Article 14 types of Layer 3 header protocol field offset value */
#define PPE_CFG_L3_TYPE_OFFSET_14_REG               (0x10E8)
/* PPE_CFG_L4_TYPE_VALUE_0 is the 0 value  Layer 4 types */
#define PPE_CFG_L4_TYPE_VALUE_0_REG                 (0x1100)
/* PPE_CFG_L4_TYPE_VALUE_0 is the 0 value MASK  Layer 4 types */
#define PPE_CFG_L4_TYPE_MASK_0_REG                  (0x1104)
/* PPE_CFG_L4_SUB_ID_0 is the 0 4 layer Dependent types configured */
#define PPE_CFG_L4_SUB_ID_0_REG                     (0x1108)
/* PPE_CFG_L4_TYPE_VALUE_1 is the 1 value  Layer 4 types */
#define PPE_CFG_L4_TYPE_VALUE_1_REG                 (0x1110)
/* PPE_CFG_L4_TYPE_VALUE_1 is the 1 value of MASK  Layer 4 types */
#define PPE_CFG_L4_TYPE_MASK_1_REG                  (0x1114)
/* PPE_CFG_L4_SUB_ID_1 is-1 configuration  Layer 4 dependent types */
#define PPE_CFG_L4_SUB_ID_1_REG                     (0x1118)
/* PPE_CFG_L4_TYPE_VALUE_2 is Layer 2 types of 4 value */
#define PPE_CFG_L4_TYPE_VALUE_2_REG                 (0x1120)
/* PPE_CFG_L4_TYPE_VALUE_2 is Layer 2 types of 4 type value MASK */
#define PPE_CFG_L4_TYPE_MASK_2_REG                  (0x1124)
/* PPE_CFG_L4_SUB_ID_2 is Layer 2 types of 4 dependent type configuration */
#define PPE_CFG_L4_SUB_ID_2_REG                     (0x1128)
/* PPE_CFG_L4_TYPE_VALUE_3 is Layer 3 types of 4 value */
#define PPE_CFG_L4_TYPE_VALUE_3_REG                 (0x1130)
/* PPE_CFG_L4_TYPE_VALUE_3 is Layer 3 types of 4 type value MASK */
#define PPE_CFG_L4_TYPE_MASK_3_REG                  (0x1134)
/* PPE_CFG_L4_SUB_ID_3 is Layer 3 types of 4 dependent type configuration */
#define PPE_CFG_L4_SUB_ID_3_REG                     (0x1138)
/* PPE_CFG_L4_TYPE_VALUE_4 is Layer 4 types of 4 value */
#define PPE_CFG_L4_TYPE_VALUE_4_REG                 (0x1140)
/* PPE_CFG_L4_TYPE_VALUE_4 is Layer 4 types of 4 type value MASK */
#define PPE_CFG_L4_TYPE_MASK_4_REG                  (0x1144)
/* PPE_CFG_L4_SUB_ID_4 is Layer 4 types of 4 dependent type configuration */
#define PPE_CFG_L4_SUB_ID_4_REG                     (0x1148)
/* PPE_CFG_L4_TYPE_VALUE_5 is the value 5 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_5_REG                 (0x1150)
/* PPE_CFG_L4_TYPE_VALUE_5 value is-5 types of layer 4 MASK */
#define PPE_CFG_L4_TYPE_MASK_5_REG                  (0x1154)
/* PPE_CFG_L4_SUB_ID_5 is-5 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_5_REG                     (0x1158)
/* PPE_CFG_L4_TYPE_VALUE_6 is the value 6 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_6_REG                 (0x1160)
/* PPE_CFG_L4_TYPE_VALUE_6 is the value 6 types of layer 4 MASK */
#define PPE_CFG_L4_TYPE_MASK_6_REG                  (0x1164)
/* PPE_CFG_L4_SUB_ID_6 to Article 6 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_6_REG                     (0x1168)
/* PPE_CFG_L4_TYPE_VALUE_7 is Layer 7 types of 4 value */
#define PPE_CFG_L4_TYPE_VALUE_7_REG                 (0x1170)
/* PPE_CFG_L4_TYPE_VALUE_7 to Article 7 types of layer 4 value MASK */
#define PPE_CFG_L4_TYPE_MASK_7_REG                  (0x1174)
/* PPE_CFG_L4_SUB_ID_7 is Layer 7 types of 4 dependent type configuration */
#define PPE_CFG_L4_SUB_ID_7_REG                     (0x1178)
/* PPE_CFG_L4_TYPE_VALUE_8 is the value 8 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_8_REG                 (0x1180)
/* PPE_CFG_L4_TYPE_VALUE_8 is the value 8 types of layer 4 MASK */
#define PPE_CFG_L4_TYPE_MASK_8_REG                  (0x1184)
/* PPE_CFG_L4_SUB_ID_8 is the 8 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_8_REG                     (0x1188)
/* PPE_CFG_L4_TYPE_VALUE_9 to Article 9 types of layer 4 value */
#define PPE_CFG_L4_TYPE_VALUE_9_REG                 (0x1190)
/* PPE_CFG_L4_TYPE_VALUE_9 to Article 9 types of layer 4 value MASK */
#define PPE_CFG_L4_TYPE_MASK_9_REG                  (0x1194)
/* PPE_CFG_L4_SUB_ID_9 to Article 9 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_9_REG                     (0x1198)
/* PPE_CFG_L4_TYPE_VALUE_10 is the 10 types of layer 4 value */
#define PPE_CFG_L4_TYPE_VALUE_10_REG                (0x11A0)
/* PPE_CFG_L4_TYPE_VALUE_10 to Article 10 types of layer 4 value MASK */
#define PPE_CFG_L4_TYPE_MASK_10_REG                 (0x11A4)
/* PPE_CFG_L4_SUB_ID_10 to Article 10 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_10_REG                    (0x11A8)
/* PPE_CFG_L4_TYPE_VALUE_11 is the value 11 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_11_REG                (0x11B0)
/* PPE_CFG_L4_TYPE_VALUE_11 to Article 11 types of layer 4 value MASK */
#define PPE_CFG_L4_TYPE_MASK_11_REG                 (0x11B4)
/* PPE_CFG_L4_SUB_ID_11 is-11 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_11_REG                    (0x11B8)
/* PPE_CFG_L4_TYPE_VALUE_12 is the value 12 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_12_REG                (0x11C0)
/* PPE_CFG_L4_TYPE_VALUE_12 value is-12 types of layer 4 MASK */
#define PPE_CFG_L4_TYPE_MASK_12_REG                 (0x11C4)
/* PPE_CFG_L4_SUB_ID_12 is-12 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_12_REG                    (0x11C8)
/* PPE_CFG_L4_TYPE_VALUE_13 is the value 13 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_13_REG                (0x11D0)
/* PPE_CFG_L4_TYPE_VALUE_13 to Article 13 types of layer 4 value MASK */
#define PPE_CFG_L4_TYPE_MASK_13_REG                 (0x11D4)
/* PPE_CFG_L4_SUB_ID_13 is-13 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_13_REG                    (0x11D8)
/* PPE_CFG_L4_TYPE_VALUE_14 is the value 14 types of layer 4 */
#define PPE_CFG_L4_TYPE_VALUE_14_REG                (0x11E0)
/* PPE_CFG_L4_TYPE_VALUE_14 to Article 14 types of layer 4 value MASK */
#define PPE_CFG_L4_TYPE_MASK_14_REG                 (0x11E4)
/* PPE_CFG_L4_SUB_ID_14 is-14 types of Layer 4 dependent configuration */
#define PPE_CFG_L4_SUB_ID_14_REG                    (0x11E8)
/* PPE_CFG_L5_TYPE_VALUE_0 is the 0 value  layer 5 types */
#define PPE_CFG_L5_TYPE_VALUE_0_REG                 (0x1200)
/* PPE_CFG_L5_TYPE_VALUE_0 is the 0 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_0_REG                  (0x1204)
/* PPE_CFG_L5_SUB_ID_0 is the 0 5 layer Dependent types configured */
#define PPE_CFG_L5_SUB_ID_0_REG                     (0x1208)
/* PPE_CFG_L5_TYPE_VALUE_1 to Layer 1 of 5 value */
#define PPE_CFG_L5_TYPE_VALUE_1_REG                 (0x1210)
/* PPE_CFG_L5_TYPE_VALUE_1 is-1 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_1_REG                  (0x1214)
/* PPE_CFG_L5_SUB_ID_1 to Layer 1 of 5 dependent type configuration */
#define PPE_CFG_L5_SUB_ID_1_REG                     (0x1218)
/* PPE_CFG_L5_TYPE_VALUE_2 is Layer 2 types of 5 value */
#define PPE_CFG_L5_TYPE_VALUE_2_REG                 (0x1220)
/* PPE_CFG_L5_TYPE_VALUE_2 is Layer 2 types of 5 type value MASK */
#define PPE_CFG_L5_TYPE_MASK_2_REG                  (0x1224)
/* PPE_CFG_L5_SUB_ID_2 is Layer 2 types of 5 dependent type configuration */
#define PPE_CFG_L5_SUB_ID_2_REG                     (0x1228)
/* PPE_CFG_L5_TYPE_VALUE_3 is Layer 3 types of 5 value */
#define PPE_CFG_L5_TYPE_VALUE_3_REG                 (0x1230)
/* PPE_CFG_L5_TYPE_VALUE_3 is Layer 3 types of 5 type value MASK */
#define PPE_CFG_L5_TYPE_MASK_3_REG                  (0x1234)
/* PPE_CFG_L5_SUB_ID_3 is Layer 3 types of 5 dependent type configuration */
#define PPE_CFG_L5_SUB_ID_3_REG                     (0x1238)
/* PPE_CFG_L5_TYPE_VALUE_4 is Layer 4 types of 5 value */
#define PPE_CFG_L5_TYPE_VALUE_4_REG                 (0x1240)
/* PPE_CFG_L5_TYPE_VALUE_4 is Layer 4 types of 5 type value MASK */
#define PPE_CFG_L5_TYPE_MASK_4_REG                  (0x1244)
/* PPE_CFG_L5_SUB_ID_4 is Layer 4 types of 5 dependent type configuration */
#define PPE_CFG_L5_SUB_ID_4_REG                     (0x1248)
/* PPE_CFG_L5_TYPE_VALUE_5 to Layer 5 types of 5 value */
#define PPE_CFG_L5_TYPE_VALUE_5_REG                 (0x1250)
/* PPE_CFG_L5_TYPE_VALUE_5 value type to Layer 5 types of 5 MASK */
#define PPE_CFG_L5_TYPE_MASK_5_REG                  (0x1254)
/* PPE_CFG_L5_SUB_ID_5 is-5 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_5_REG                     (0x1258)
/* Article 6 is PPE_CFG_L5_TYPE_VALUE_6 value  layer 5 types */
#define PPE_CFG_L5_TYPE_VALUE_6_REG                 (0x1260)
/* Article 6 is PPE_CFG_L5_TYPE_VALUE_6 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_6_REG                  (0x1264)
/* PPE_CFG_L5_SUB_ID_6 to Article 6 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_6_REG                     (0x1268)
/* PPE_CFG_L5_TYPE_VALUE_7 is Layer 7 types of 5 value */
#define PPE_CFG_L5_TYPE_VALUE_7_REG                 (0x1270)
/* PPE_CFG_L5_TYPE_VALUE_7 is Layer 7 types of 5 type value MASK */
#define PPE_CFG_L5_TYPE_MASK_7_REG                  (0x1274)
/* PPE_CFG_L5_SUB_ID_7 is Layer 7 types of 5 dependent type configuration */
#define PPE_CFG_L5_SUB_ID_7_REG                     (0x1278)
/* PPE_CFG_L5_TYPE_VALUE_8 is the value 8 types of 5 layer */
#define PPE_CFG_L5_TYPE_VALUE_8_REG                 (0x1280)
/* Article 8 is PPE_CFG_L5_TYPE_VALUE_8 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_8_REG                  (0x1284)
/* PPE_CFG_L5_SUB_ID_8 is the 8 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_8_REG                     (0x1288)
/* PPE_CFG_L5_TYPE_VALUE_9 to Article 9 5 layer type value */
#define PPE_CFG_L5_TYPE_VALUE_9_REG                 (0x1290)
/* Article 9 is PPE_CFG_L5_TYPE_VALUE_9 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_9_REG                  (0x1294)
/* PPE_CFG_L5_SUB_ID_9 to Article 9 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_9_REG                     (0x1298)
/* PPE_CFG_L5_TYPE_VALUE_10 is the value 10 types of 5 layer */
#define PPE_CFG_L5_TYPE_VALUE_10_REG                (0x12A0)
/* PPE_CFG_L5_TYPE_VALUE_10 to Article 10 types of 5 layer value MASK */
#define PPE_CFG_L5_TYPE_MASK_10_REG                 (0x12A4)
/* PPE_CFG_L5_SUB_ID_10 to Article 10 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_10_REG                    (0x12A8)
/* PPE_CFG_L5_TYPE_VALUE_11 to No. 11 types of 5 layer configuration value */
#define PPE_CFG_L5_TYPE_VALUE_11_REG                (0x12B0)
/* Article 11 is PPE_CFG_L5_TYPE_VALUE_11 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_11_REG                 (0x12B4)
/* PPE_CFG_L5_SUB_ID_11 to Article 11 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_11_REG                    (0x12B8)
/* PPE_CFG_L5_TYPE_VALUE_12 to No. 12 types of 5 layer configuration value */
#define PPE_CFG_L5_TYPE_VALUE_12_REG                (0x12C0)
/* PPE_CFG_L5_TYPE_VALUE_12 value is-12 types of 5 layer MASK */
#define PPE_CFG_L5_TYPE_MASK_12_REG                 (0x12C4)
/* PPE_CFG_L5_SUB_ID_12 is-12 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_12_REG                    (0x12C8)
/* PPE_CFG_L5_TYPE_VALUE_13 to No. 13 types of 5 layer configuration value */
#define PPE_CFG_L5_TYPE_VALUE_13_REG                (0x12D0)
/* Article 13 is PPE_CFG_L5_TYPE_VALUE_13 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_13_REG                 (0x12D4)
/* PPE_CFG_L5_SUB_ID_13 to Article 13 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_13_REG                    (0x12D8)
/* Article 14 is PPE_CFG_L5_TYPE_VALUE_14 value  layer 5 types */
#define PPE_CFG_L5_TYPE_VALUE_14_REG                (0x12E0)
/* Article 14 is PPE_CFG_L5_TYPE_VALUE_14 value MASK  layer 5 types */
#define PPE_CFG_L5_TYPE_MASK_14_REG                 (0x12E4)
/* PPE_CFG_L5_SUB_ID_14 to Article 14 types of 5-dependent configuration */
#define PPE_CFG_L5_SUB_ID_14_REG                    (0x12E8)
/* PPE_CFG_QOS_TBL0_KEY_OFFSET is QOS table key generated configuration 0 register.
 * 0x4100~0x4138 are 0~7 configuration tables
 */
#define PPE_CFG_QOS_TBL_KEY_OFFSET_0_REG            (0x4100)
/* PPE_CFG_QOS_TBL0_KEY_OFFSET is QOS table key generated configuration 0 register.
 * 0x4100~0x4138 are 0~7 configuration tables
 */
#define PPE_CFG_QOS_TBL_KEY_OFFSET_1_REG            (0x4108)
/* PPE_CFG_GRP_VMID_TBL0_KEY_OFFSET0 is to generate GRP and VMID table configuration
 * register 0 of the key is generated. 0x5D00~0x5D50 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0_0_REG      (0x5D00)
/* PPE_CFG_GRP_VMID_TBL0_KEY_OFFSET0 is to generate GRP and VMID table configuration
 * register 0 of the key is generated. 0x5D00~0x5D50 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0_1_REG      (0x5D08)
/* PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0 is to generate GRP and VMID table configuration
 * register 1 key is generated. 0x5D04~0x5D54 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET1_0_REG      (0x5D04)
/* PPE_CFG_GRP_VMID_TBL_KEY_OFFSET0 is to generate GRP and VMID table configuration
 * register 1 key is generated. 0x5D04~0x5D54 are 0~10 configuration tables
 */
#define PPE_CFG_GRP_VMID_TBL_KEY_OFFSET1_1_REG      (0x5D0C)

/* Packet RX descriptor */
struct receive_descripte_ppe {
	/* Packets  For a linked list storage structure, this field is set to 0. */
	unsigned int    prev_data_addr_31_0;

	/* Packets  For a linked list storage structure, this field is set to 0. */
	unsigned int    next_data_addr_31_0;

	/* IP address of the descriptor (5:0 should be 0, press Cache-Line aligned). */
	unsigned int    ref_itself_addr_31_0;

	/* Indicates the packets stored in the buffer data length. Unit: byte. */
	unsigned int data_lenth : 16;
	/* Packet data relative to the descriptor start address offset. Unit: byte. */
	unsigned int data_offset : 16;

	/* The indication packet. The value is 1. */
	unsigned int    rel_flag;

	/* Number of packets is referenced. The value is 1. */
	unsigned int    rel_cnt;

	/* Bit[39:36] domain. It has a fixed value of 0 is reserved. */
	unsigned int prev_data_addr_39_32 : 8;
	/* Bit[39:36] domain. It has a fixed value of 0 is reserved. */
	unsigned int next_data_addr_39_32 : 8;
	/* Bit[39:36] domain. It has a fixed value of 0 is reserved. */
	unsigned int ref_itself_addr_39_32 : 8;
	/* Reserved */
	unsigned int reserved1 : 4;
	/* Indicates the descriptor extension. The value is 1. */
	unsigned int append_type : 4;

	/* The cache node type indication. [2'b00: single node. First node  2'b01: linked list structure.
	 * 2'b10: linked list tail node. 2'b11: linked list structure intermediate nodes ]
	 */
	unsigned int fi : 2;
	/* Reserved */
	unsigned int reserved2 : 6;
	/* The initial data in the cache in the entire packet offset. */
	unsigned int chain_offset : 24;

	/* The entire packet buffer. If the number of consumed more than 1,
	 * indicating that the number of the linked list structure to store the entire packet segment.
	 */
	unsigned int num_in_chain : 8;
	/* The length of packets. Unit: byte. Bit[23:16] domain. It has a fixed value of 0 is reserved. */
	unsigned int chain_length : 24;

	/* Compressed timestamp */
	unsigned int    timestamp;

	/* Packet header to the IP header offset. The unit is byte. */
	unsigned int ip_offset : 8;
	/* Reserved */
	unsigned int reserved3 : 2;
	/* RX descriptor validity flag. It is used only for debugging. */
	unsigned int vld : 1;
	/* IP fragment ID. */
	unsigned int ip_frag : 1;
	/* Five-layer packet protocol type and code. */
	unsigned int l5_id : 4;
	/* Layer 4 protocol type. */
	unsigned int l4_id : 4;
	/* Layer 3 packet type. */
	unsigned int l3_id : 4;
	/* ID of the VLAN packets. */
	unsigned int pkt_vlan : 2;
	/* Layer 2 packet type ID. */
	unsigned int dmac_type : 2;
	/* Layer 4 parsing error flag. */
	unsigned int l4_err : 1;
	/* Layer 3 parsing error flag. */
	unsigned int l3_err : 1;
	/* Layer 2 packet parsing error flag. */
	unsigned int l2_err : 1;
	/* The received packet is truncated flag. */
	unsigned int pkt_drop : 1;

	/* VLAN Priority fields of the packets. */
	unsigned int vlan_priority : 3;
	/* CFI field of the VLAN packet. */
	unsigned int vlan_cfi : 1;
	/* VLAN_ID field of the VLAN packet. */
	unsigned int vlan_id : 12;
	/* Reserved */
	unsigned int reserved4 : 12;
	/* FP_CRC verification results. */
	unsigned int fp_crc : 16;
	/* FP frame indication. */
	unsigned int fp : 16;

	/* packet timestamp in nanoseconds */
	unsigned int    timestamp_nanosecond;

	/* packet timestamp in seconds */
	unsigned int    timestamp_second;

	/* Reserved */
	unsigned int    reserved5;

	/* Reserved */
	unsigned int    reserved6;
};

/* Packet Transmit Descriptor */
struct tx_descript {
	/* Reserved */
	unsigned int    reserved1;

	/* Packets  For a linked list storage structure, this field is set to 0. */
	unsigned int    next_data_addr_31_0;

	/* IP address of the descriptor (5:0 should be 0, press Cache-Line aligned). */
	unsigned int    ref_itself_addr_31_0;

	/* Indicates the packets stored in the buffer data length. Unit: byte. */
	unsigned int data_lenth : 16;
	/* Packet data relative to the descriptor start address offset. Unit: byte. */
	unsigned int data_offset : 16;

	/* Reserved */
	unsigned int    reserved2;

	/* Reserved */
	unsigned int    reserved3;

	/* Reserved */
	unsigned int reserved4 : 8;
	/* Bit[39:36] domain. It has a fixed value of 0 is reserved. */
	unsigned int prev_data_addr_39_32 : 8;
	/* Bit[39:36] domain. It has a fixed value of 0 is reserved. */
	unsigned int next_data_addr_39_32 : 8;
	/* Reserved */
	unsigned int reserved5 : 8;

	/* Reserved */
	unsigned int    reserved6;

	/* The entire packet buffer. If the number of consumed more than 1,
	 * indicating that the number of the linked list structure to store the entire packet segment.
	 */
	unsigned int num_in_chain : 8;
	/* Reserved */
	unsigned int reserved7 : 24;

	/* Reserved */
	unsigned int    reserved8;

	/* Packet header to the IP header offset. The unit is byte. */
	unsigned int ip_offset : 8;
	/* When sending packets to control whether the Layer 4 additional Checksum. */
	unsigned int l4_cs : 1;
	/* When sending packets, control whether the additional Checksum. Layer 3 */
	unsigned int l3_cs : 1;
	/* Reserved */
	unsigned int reserved9 : 22;

	/* Reserved */
	unsigned int reserved10 : 11;
	unsigned int pool_num : 5;
	/* Loopback packet flag. */
	unsigned int lb : 1;
	/* 1588 packet sending sends time information indication signal. */
	unsigned int bi : 1;
	/* 1588 packet sending indication information. */
	unsigned int ptpm : 2;
	/* The packets are involved in Y.1731 flow 2 statistics. */
	unsigned int yvld2 : 1;
	/* The packets are involved in Y.1731 flow 1 statistics. */
	unsigned int yvld1 : 1;
	/* whether to add the packet statistics for Y.1731). */
	unsigned int asts : 1;
	/* whether to add the packet timestamp(for Y.1731). */
	unsigned int astp : 1;
	/* After sending whether to "WB_Addr" write 0 to the specified address. */
	unsigned int cl : 1;
	/* The PPE transmits the packets, you can choose whether to perform Invalidate operations on the Cache. */
	unsigned int ri : 1;
	/* Read Allocate (Read-Allocate) flag to control whether to send data read L3 cache. */
	unsigned int ra : 1;
	unsigned int lc : 1;
	/* Reserved */
	unsigned int reserved11 : 4;

	/* Feedback HD 0 address  Data transmission is complete. */
	unsigned int    wb_addr_31_0;

	/* Reserved */
	unsigned int reserved12 : 24;
	/* Bit[39:36] domain. It has a fixed value of 0 is reserved. */
	unsigned int wb_addr_39_32 : 8;

	/* Reserved */
	unsigned int    reserved13;

	/* Reserved */
	unsigned int    reserved14;
};

/* Storage format control parameters   Receive packets */
typedef struct tag_ppe_pkt_store_ctrl_cfg {
	/* The first before receiving buffer header packet descriptors reserved number of cache line */
	unsigned int cf_rxbuf_1st_skip1;
	/* The first After receiving buffer header packet descriptors reserved number of cache line */
	unsigned int cf_rxbuf_1st_skip_size2;
	/* a first receiving buffer header reserved number of cache line */
	unsigned int cf_buf_n1st_skip;
	/* The receiving and buffering data packet header alignment blank bytes */
	unsigned int cf_rx_align_num;
} ppe_pkt_store_ctrl_cfg_s;

/* Packet Format parameter */
typedef struct tag_ppe_pkt_parse_mode_cfg {
	/* If the input packets skip area length before */
	unsigned int cf_skip1_len;
	/* If the input packets skip area length before */
	unsigned int cf_skip2_len;
	/* Packet parsing mode */
	unsigned int cf_parse_mode;
} ppe_pkt_parse_mode_cfg_s;


/******************************************************************************/
/* GMAC GE register defined */
/******************************************************************************/
/* full-duplex half duplex mode register */
#define GE_DUPLEX_TYPE_REG					(0x8)
/* FD_FC_TYPE type domain register for flow control frames. */
#define GE_FD_FC_TYPE_REG					(0xC)
/* FC_TX_TIMER is the flow control time parameter register. */
#define GE_FC_TX_TIMER_REG					(0x1C)
/* FD_FC_ADDR_LOW is flow control frame 1 destination address register. */
#define GE_FD_FC_ADDR_LOW_REG				(0x20)
/* FD_FC_ADDR_HIGH is destination address register 2 flow control frames. */
#define GE_FD_FC_ADDR_HIGH_REG				(0x24)
/* IPG_TX_TIMER is Transmit IPG register. */
#define GE_IPG_TX_TIMER_REG					(0x30)
/* PAUSE_THR IPG register for sending flow control frames. */
#define GE_PAUSE_THR_REG					(0x38)
/* MAX_FRM_SIZE is max frame length register. */
#define GE_MAX_FRM_SIZE_REG					(0x3C)
/* PORT_MODE is a port status register. */
#define GE_PORT_MODE_REG					(0x40)
/* PORT_EN is the channel enable register. */
#define GE_PORT_EN_REG						(0x44)
/* PAUSE_EN is flow control enable register. */
#define GE_PAUSE_EN_REG						(0x48)
/* SHORT_RUNTS_THR is ultra-short frame threshold register. */
#define GE_SHORT_RUNTS_THR_REG				(0x50)
/* TRANSMIT_CONTROL is common configuration register. */
#define GE_TRANSMIT_CONTROL_REG				(0x60)
/* REC_FILT_CONTROL is Filter control register for the receive frame. */
#define GE_REC_FILT_CONTROL_REG				(0x64)
/* RX_OCTETS_TOTAL_OK is the byte count register for the received valid frames. */
#define GE_RX_OCTETS_TOTAL_OK_REG			(0x80)
/* RX_OCTETS_BAD is error frames received byte count register. */
#define GE_RX_OCTETS_BAD_REG				(0x84)
/* Count unicast frames received by MAC RX_UC_PKTS is register. */
#define GE_RX_UC_PKTS_REG					(0x88)
/* RX_MC_PKTS is received multicast frames count register. */
#define GE_RX_MC_PKTS_REG					(0x8C)
/* RX_BC_PKTS is Frame count register of the received broadcast frames. */
#define GE_RX_BC_PKTS_REG					(0x90)
/* RX_PKTS_64OCTETS is received frame length is 64byte Count register. */
#define GE_RX_PKTS_64OCTETS_REG				(0x94)
/* RX_PKTS_65TO127OCTETS is received frame length is 65 ~127byte Count register. */
#define GE_RX_PKTS_65TO127OCTETS_REG		(0x98)
/* RX_PKTS_128TO255OCTETS is received frame length is 128 ~255byte Count register. */
#define GE_RX_PKTS_128TO255OCTETS_REG		(0x9C)
/* RX_PKTS_255TO511OCTETS is received frame length is 256 ~511byte Count register. */
#define GE_RX_PKTS_255TO511OCTETS_REG		(0xA0)
/* RX_PKTS_512TO1023OCTETS is received frame length is 512 ~1023byte Count register. */
#define GE_RX_PKTS_512TO1023OCTETS_REG		(0xA4)
/* RX_PKTS_1024TO1518OCTETS is an RX frame length is 1024~1518byte Count register. */
#define GE_RX_PKTS_1024TO1518OCTETS_REG		(0xA8)
/* RX_PKTS_1519TOMAXOCTETS is received frame length of 1519max  byte frame count register. */
#define GE_RX_PKTS_1519TOMAXOCTETS_REG		(0xAC)
/* RX_FCS_ERRORS is CRC check error frames received by count register. */
#define GE_RX_FCS_ERRORS_REG				(0xB0)
/* RX_TAGGED is received with TAG frame count register. */
#define GE_RX_TAGGED_REG					(0xB4)
/* RX_DATA_ERR is the RX data error frame count register. */
#define GE_RX_DATA_ERR_REG					(0xB8)
/* RX_ALIGN_ERRORS is receiving data is byte alignment error frame count register. */
#define GE_RX_ALIGN_ERRORS_REG				(0xBC)
/* RX_LONG_ERRORS is an RX frame length exceeds max length 1 frame count register. */
#define GE_RX_LONG_ERRORS_REG				(0xC0)
/* RX_JABBER_ERRORS is an RX frame length exceeds max Count register 2 of. */
#define GE_RX_JABBER_ERRORS_REG				(0xC4)
/* RX_PAUSE_MACCONTROL_FRAMCOUNTER count register for the received flow control frames. */
#define GE_RX_PAUSE_MACCONTROL_FRAMCOUNTER_REG			(0xC8)
/* RX_UNKNOWN_MACCONTROL_FRAMCOUNTER is MAC receives a flow control frame count register. */
#define GE_RX_UNKNOWN_MACCONTROL_FRAMCOUNTER_REG         (0xCC)
/* RX_VERY_LONG_ERR_CNT is received long frame count register. */
#define GE_RX_VERY_LONG_ERR_CNT_REG			(0xD0)
/* RX_RUNT_ERR_CNT is received frame 64byte greater than or equal to 12byte Count register. */
#define GE_RX_RUNT_ERR_CNT_REG				(0xD4)
/* RX_SHORT_ERR_CNT is an RX frame length is less than 96bit frame count register. */
#define GE_RX_SHORT_ERR_CNT_REG				(0xD8)
/* Statistics  filtered packets received */
#define GE_RX_FILT_PKT_CNT_REG				(0xE8)
/* Indicates the statistics of received filtered byte. */
#define GE_RX_OCTETS_TOTAL_FILT_REG			(0xEC)
/* OCTETS_TRANSMITTED_OK is good packets are successfully sent byte count register. */
#define GE_OCTETS_TRANSMITTED_OK_REG		(0x100)
/* OCTETS_TRANSMITTED_BAD is successfully sent bad byte count register. */
#define GE_OCTETS_TRANSMITTED_BAD_REG		(0x104)
/* TX_UC_PKTS is the number of sent unicast frames register. */
#define GE_TX_UC_PKTS_REG					(0x108)
/* TX_MC_PKTS is a multicast frame count register. */
#define GE_TX_MC_PKTS_REG					(0x10C)
/* TX_BC_PKTS is Frame count register of the transmitted broadcast frames. */
#define GE_TX_BC_PKTS_REG					(0x110)
/* TX_PKTS_64OCTETS is TX frame length is 64byte Count register. */
#define GE_TX_PKTS_64OCTETS_REG				(0x114)
/* TX_PKTS_65TO127OCTETS is TX frame length is 65 ~127byte Count register. */
#define GE_TX_PKTS_65TO127OCTETS_REG		(0x118)
/* TX_PKTS_128TO255OCTETS is TX frame length is 128 ~255byte Count register. */
#define GE_TX_PKTS_128TO255OCTETS_REG		(0x11C)
/* TX_PKTS_255TO511OCTETS is TX frame length is 256~511byte Count register. */
#define GE_TX_PKTS_255TO511OCTETS_REG		(0x120)
/* TX_PKTS_512TO1023OCTETS is TX frame length is 512 ~1023byte section frame count register. */
#define GE_TX_PKTS_512TO1023OCTETS_REG		(0x124)
/* TX_PKTS_1024TO1518OCTETS is TX frame length is 1024~1518byte Count register. */
#define GE_TX_PKTS_1024TO1518OCTETS_REG		(0x128)
/* TX_PKTS_1519TOMAXOCTETS is the TX frame length is greater than 1519byte Count register. */
#define GE_TX_PKTS_1519TOMAXOCTETS_REG		(0x12C)
/* TX_EXCESSIVE_LENGTH_DROP is exceeds the preset max frame length
 * in the sending failure count register.
 */
#define GE_TX_EXCESSIVE_LENGTH_DROP_REG		(0x14C)
/* TX_UNDERRUN is internal error occurs during frame transmission sent due to count. */
#define GE_TX_UNDERRUN_REG					(0x150)
/* TX_TAGGED is a VLAN frame count register. */
#define GE_TX_TAGGED_REG					(0x154)
/* TX_CRC_ERROR is a frame length correct CRC error frame count register. */
#define GE_TX_CRC_ERROR_REG					(0x158)
/* TX_PAUSE_FRAMES count register for sending PAUSE frames. */
#define GE_TX_PAUSE_FRAMES_REG				(0x15C)
/* LED_MOD is indicator mode control register. */
#define GE_LED_MOD_REG						(0x16C)
/* LINE_LOOP_BACK is MAC line-side loopback register. */
#define GE_LINE_LOOP_BACK_REG				(0x1A8)
/* CF_CRC_STRIP is CRC strip enable register. */
#define GE_CF_CRC_STRIP_REG					(0x1B0)
/* MODE_CHANGE_EN is the port mode change enable register. */
#define GE_MODE_CHANGE_EN_REG				(0x1B4)
/* Supplementary LOOP_REG is a loopback register. */
#define GE_LOOP_REG							(0x1DC)
/* RECV_CONTROL is an RX control register. */
#define GE_RECV_CONTROL_REG					(0x1E0)
/* VLAN_CODE is VLAN Code register. */
#define GE_VLAN_CODE_REG					(0x1E8)
/* RX_OVERRUN_CNT is FIFO overrun count register. */
#define GE_RX_OVERRUN_CNT_REG				(0x1EC)
/* RX_LENGTHFIELD_ERR_CNT is including PAD frame count register. */
#define GE_RX_LENGTHFIELD_ERR_CNT_REG		(0x1F4)
/* RX_FAIL_COMMA_CNT is byte delimit COMMA count register. */
#define GE_RX_FAIL_COMMA_CNT_REG			(0x1F8)
/* STATION_ADDR_LOW is the local MAC address 1 0 register. */
#define GE_STATION_ADDR_LOW_0_REG			(0x200)
/* STATION_ADDR_HIGH is the local MAC address 2 0 register. */
#define GE_STATION_ADDR_HIGH_0_REG			(0x204)
/* STATION_ADDR_LOW is the local MAC address 1 1 register. */
#define GE_STATION_ADDR_LOW_1_REG			(0x208)
/* STATION_ADDR_HIGH is the local MAC address 2 1 register. */
#define GE_STATION_ADDR_HIGH_1_REG			(0x20C)
/* STATION_ADDR_LOW is the local MAC address 1 2 register. */
#define GE_STATION_ADDR_LOW_2_REG			(0x210)
/* STATION_ADDR_HIGH is the local MAC address 2 2 register. */
#define GE_STATION_ADDR_HIGH_2_REG			(0x214)
/* STATION_ADDR_LOW is the local MAC address 1 3 register. */
#define GE_STATION_ADDR_LOW_3_REG			(0x218)
/* STATION_ADDR_HIGH is the local MAC address 2 3 register. */
#define GE_STATION_ADDR_HIGH_3_REG			(0x21C)
/* STATION_ADDR_LOW is the local MAC address 1 4 register. */
#define GE_STATION_ADDR_LOW_4_REG			(0x220)
/* STATION_ADDR_HIGH is the local MAC address 2 4 register. */
#define GE_STATION_ADDR_HIGH_4_REG			(0x224)
/* STATION_ADDR_LOW is the local MAC address 1 5 register. */
#define GE_STATION_ADDR_LOW_5_REG			(0x228)
/* STATION_ADDR_HIGH is the local MAC address 2 5 register. */
#define GE_STATION_ADDR_HIGH_5_REG			(0x22C)
/* STATION_ADDR_LOW is the local MAC address 0 1 mask register. */
#define GE_STATION_ADDR_LOW_MSK_0_REG		(0x230)
/* STATION_ADDR_HIGH is the local MAC address 0 2 mask register. */
#define GE_STATION_ADDR_HIGH_MSK_0_REG		(0x234)
/* STATION_ADDR_LOW is the local MAC address 1 1 mask register. */
#define GE_STATION_ADDR_LOW_MSK_1_REG		(0x238)
/* STATION_ADDR_HIGH is the local MAC address 1 2 mask register. */
#define GE_STATION_ADDR_HIGH_MSK_1_REG		(0x23C)
/* SKIP_LEN is header does not parse the field length. */
#define GE_MAC_SKIP_LEN_REG					(0x240)
/* DMAC is share 32 characters without local MAC address mask enable. */
#define GE_DMAC_EN_REG						(0x370)
/* DMAC to share 32 with local MAC address mask enable. . */
#define GE_DMAC_WITH_MSK_EN_REG				(0x374)
/* Specifies the loopback packet priority-level configuration. */
#define GE_TX_LOOP_PKT_PRI_REG				(0x378)

/******************************************************************************/
/* Definition  SYSCtl register */
/******************************************************************************/
/* MAC soft reset request control register */
#define SC_MAC_RESET_REQ					(0x0238)
/* To  MAC soft reset request control register */
#define SC_MAC_RESET_DREQ					(0x023C)
/* MAC configuration soft reset request control register */
#define SC_MAC_CFG_RESET_REQ					(0x0230)
/* MAC configuration to soft reset request control register */
#define SC_MAC_CFG_RESET_DREQ					(0x0234)
/* Soft reset request control register  GE */
#define SC_GE_RESET_REQ						(0x0220)
/* Soft reset request control register  GE */
#define SC_GE_RESET_DREQ					(0x0224)
/* PPE soft reset request control register */
#define SC_PPE_RESET_REQ					(0x0268)
/* PPE to soft reset request control register */
#define SC_PPE_RESET_DREQ					(0x026C)
#define IOMG058							(0xe4)

#endif
